T Flip-Flop
Master-Slave Flip-Flop
PREVIOUS <<- SR Flip-Flop
PREVIOUS <<- SR Flip-Flop
D Flip-Flop
The D flip-flop shown in
Figure.5 is a modification of the clocked
SR flip-flop.
The
D input goes directly into the
S input and the
complement of the D input goes
to the
R input . The D input is sampled during the occurrence of a clock pulse.
If it is
1, the flip-flop is switched to the
set state (unless it was already set).
If it is
0, the flip-flop switches to the
clear state .
(a) Logic diagram
(c) Graphical Symbol
Figure 5. Clocked D flip-flop
(b) Transition Table
The T flip-flop is a
single input version of the JK flip-flop. As shown in
Figure 6 ,
the T flip-flop is obtained from the JK type if both inputs are tied together.
The output of the T flip-flop "
toggles" with each clock pulse.
(a) Logic diagram
(c) Graphical Symbol
Figure 6. Clocked T flip-flop
(b) Transition Table
A master-slave flip-flop is constructed from
two seperate flip-flops. One circuit
serves as a
master and the other as a
slave . The logic diagram of an SR flip-flop
is shown in
Figure 7 . The master flip-flop is
enabled on the positive edge of
the clock pulse
CP and the slave flip-flop is
disabled by the inverter.
The information at the external R and S inputs is transmitted to the master
flip-flop. When the pulse returns to
0, the
master flip-flop is
disabled
and the
slave flip-flop is
enabled . The slave flip-flop then goes to the
same state as the master flip-flop.
Figure 7. Logic diagram of a master-slave flip-flop
The timing relationship is shown in
Figure 8 and is assumed that the flip-flop
is in the clear state prior to the occurrence of the clock pulse. The output
state of the master-slave flip-flop occurs on the
negative transition of the
clock pulse. Some master-slave flip-flops change output state on the
positive
transition of the clock pulse by having an additional inverter between the
CP terminal and the input of the master.
Figure 8. Timing relationship in a master slave flip-flop
